1. Field of the Invention
The present invention generally relates to a semiconductor device which is formed on an SOI (Silicon On Insulator) substrate and has a source-tie structure.
2. Description of the Related Art
A semiconductor device such as an nMOS (Metal Oxide Semiconductor) device or a pMOS device formed on an SOI substrate includes a semiconductor layer of thin silicon (Si) formed on a silicon substrate, with a buried oxide film (an insulating layer) interposed between the semiconductor layer and the silicon substrate. Since the semiconductor layer is surrounded by a device isolating layer, a channel region of the device is in a floating state. Therefore, carriers are produced responsive to impact ions at a drain end of a channel region of the device, and the carriers function as a base current that turns on a parasitic diode. In the case of an nMOS device the carriers are holes, and in the case of a pMOS device the carriers are electrons. In drain current (Id)−gate voltage (Vg) characteristics, when a drain voltage (Vd) is increased, an S factor (Subthreshold swing S) is reduced to be smaller than a theoretical value. As a result, the carriers produced responsive to a single latch-up phenomenon that a threshold voltage (Vth) is precipitously reduced, and to impact ionization at the drain end. The carriers are stored in the channel region, and a potential in the channel region fluctuates. Given the situation, in Id−Vd characteristics, a drain current is precipitously increased in a region where a drain voltage is high. This is called a kink phenomenon. For more details, a substrate floating effect such a kink phenomenon usually occurs in the region where a drain voltage is high.
Furthermore, in an analog circuit using a gate voltage which is approximately 1 V higher than a threshold voltage, since operation when a change in a drain current with respect to a drain voltage is large is a problem, a further increase in the drain current due to the kink phenomenon becomes an even greater problem in particular.
Extracting the carriers stored in the channel region by use of a body-tie structure or a source-tie structure is effective to suppress the substrate floating effect. However, in a body-tie structure as shown in FIGS. 5 and 10 of Japanese Patent Application Laid-Open No. 2003-174172 for example, where the carriers are extracted from an end of the channel region in a gate width direction or in a source-tie structure, when gate width is long, the effect of extracting the carriers stored in the channel region is reduced even though the carriers are extracted from both ends. Hence, applying such structures to devices with an extremely large gate width is difficult.
When a conventional semiconductor device having a source-tie structure is an nMOS device, a gate electrode is formed on a rectangular semiconductor layer of an SOI substrate, and a gate insulating film is sandwiched therebetween in such a manner that the gate electrode crosses the semiconductor layer. An N-type drain layer is formed on one side of the semiconductor layer and an N-type source layer is formed on the other side, and a P-type channel region is formed in the semiconductor layer below the gate electrode between the source layer and the drain layer. Furthermore, P-type impurity diffusing regions extending in a gate length direction and having a concentration higher than that in the channel region are formed at a plurality of positions in the channel region, in the gate width direction. P-type body contact regions which extend in a gate length direction, are respectively connected with the impurity diffusing regions and have a concentration higher than that of the impurity diffusing regions, and are formed in the source layer to form a comb-like source-tie structure. Carriers stored in the channel region are thus extracted by means of this structure, which is shown and described in Japanese Patent Application Laid-open No. 2003-17472, particularly on page 9, paragraph 0071 to page 10, paragraph 0078, and in FIGS. 13 and 14.
However, in the conventional technology, the P-type impurity diffusing regions extending in the gate length direction and having a concentration higher than that of the channel region, are formed at a plurality of positions in the P-type channel region along the gate width direction. The P-type body contact regions which extend in the gate length direction are respectively connected with the impurity diffusing regions and have a concentration higher than that of the impurity diffusing regions, and are formed on the source layer side, thereby forming the source-tie structure. A resist mask used to form the impurity diffusing layers which are the same conductivity type as the channel region, and a resist mask used to form the gate electrode, must be accurately positioned. If alignment displacement occurs during superpositioning of the resist masks such that the impurity diffusing layers are shifted to the drain layer side, there arises a problem that punch-through occurs, and consequently drain current cannot be controlled using gate voltage. If the masks are designed in advance primarily to avoid alignment displacement during superpositioning of the resist masks, reduction of gate length is difficult, and the semiconductor device is disadvantageously increased in size.
Additionally, a sidewall is generally formed on a side surface of a gate electrode. An insulating material such as a silicon oxide (SiO2) or a silicon nitride (Si3N4) used to form the sidewall is deposited on the semiconductor layer. The insulating material and the gate insulating film are anisotropically etched to expose an upper surface of the gate electrode and an upper surface of the semiconductor layer, thereby forming the sidewall. In this case, there arises a problem that too much of the upper surface of the gate electrode may be removed due to over-etching. A film thickness of the body contact regions which are the same conductivity type as the channel region and formed on the source layer side is thus reduced, parasitic resistance is increased, and the effect of extracting the carriers stored in the channel region is reduced. This becomes particularly prominent in case of the SOI substrate in which film thickness of the semiconductor layer is small.